HOW-TO: PROGRAMMABLE LOGIC gadgets (CPLD)
complex programmable logic gadgets (CPLDs) contain the building blocks for numerous 7400-serries logic ICs. total circuits can be designed on a PC as well as then uploaded to a CPLD for immediate implementation. A microcontroller linked to a CPLD is like a microcontroller paired with a reprogrammable circuit card as well as a completely stocked electronics store.
At very first we weren’t sure of the wide charm as well as application of CPLDs in hobbyist projects, however we’ve been convinced. A custom logic gadget can get rid of days of reading datasheets, discovering the perfect logic IC combination, as well as then waiting on chips to arrive. Circuit boards are easier with CPLDs since a single chip with programmable pin placement can replace 100s of private logic ICs. Circuit errors can be corrected by uploading a new design, rather than etching as well as stuffing a new circuit board. CPLDs are fast, with reaction times starting at 100MHz. in spite of their extreme versatility, CPLDs are a mature innovation with chips starting at $1.
We’ve got a home-etchable, self programming advancement board to get you started. Don’t worry, this board has a serial port interface for working with the CPLD, as well as doesn’t need a separate (usually parallel port) JTAG programmer.
Intro to CPLDs
When to utilize a CPLD
Consider utilizing a CPLD when a style requires more than one 7400 series logic ICs. A CPLD will be cheaper, faster, as well as can be programmed with your perfect pin-out configuration for easier PCBs.
Use a CPLD in tricky styles that may need a number of iterations. It’s easier to style a new circuit in software application as well as upload it to the CPLD than it is to design, etch, as well as stuff a new circuit board.
For maximum speed as well as immediate response, select a CPLD. The difference in speed is amazing; CPLDs begin at a 100MHz, while microcontrollers respond to interrupts at a few MHz. CPLD styles type circuits that react to outside stimulus, reactions happen almost instantaneously. A microcontroller executes code to react to events, even interrupt routines have comparatively high latency.
CPLD vs FPGA
FPGAs are much better understood than CPLDs, however they share many characteristics. This analogy isn’t perfect, however we like it: where FPGAs are a reprogrammable processor core, a CPLD is a reprogrammable circuit card or breadboard. FPGAs replace microcontrollers, memory, as well as other components. CPLDs take in logic ICs, as well as work well with a microcontroller.
Manufacturers
Altera as well as Xilinx, the biggest CPLD manufacturers, are much better understood for their FPGAs. Lattice Semiconductor is one more big CPLD manufacturer with less neighborhood following. Atmel makes pin-compatible versions of old industry-standard CPLDs.
If you plan to work at 5volts, your choices are limited. Xilinx XC9500 CPLDs are still offered as new old stock, however expense four times more than newer 3.3volt equivalents. Atmel’s ATF1502 series works at 5volts, however they don’t offer a free advancement environment.
At 3.3volts there’s more options, however new CPLDs progressively have a core that runs at 2.5volts, 1.8volts, or lower. The Altera MAXII as well as the Xilinx XC9500XL series are most likely the most prominent 3.3volt CPLDs. Xilinx likewise makes the CoolrunnerII CPLD, however it only is available in a TQFP bundle as well as needs a separate 1.8volt supply for the core.
Packages
Most manufacturers offer one or two CPLDs in a hobbyist friendly PLCC 44 package, though this is starting to disappear. PLCC is an SOIC-sized surface install chip with pins on all four sides. PLCC44 sockets are commonly offered in through-hole as well as SMD versions. Unfortunately, newer CPLD households are starting to get rid of the PLCC bundle as well as offer only 44 pin as well as larger TQFP chips, such as Xilinx’s CoolrunnerII.
Development environments
Most manufacturers offer a free advancement atmosphere that supports style entry utilizing simple schematics, in addition to Verilog or VHDL. many won’t support the latest FPGAs in the free version, however we only requirement the CPLD parts anyway. Altera has Quartus, Xilinx has ISE, as well as Lattice has ispLever. Atmel has ProChip designer for the ATF15xx series, however they only offer a 6month trial permit — which they wouldn’t really provide us.
Programmers
The advancement board we present doesn’t requirement a separate JTAG programmer since the pic microcontroller already programs the CPLD. If you want an outside programmer, the cheapest are the parallel port programmers: Parallel cable III for Xilinx as well as BytleBlaster for Altera. affordable clones, as well as schematics, are offered at SparkFun. The OpenOCD is a generic USB JTAG programmer that will work with many CPLDs, FPGAs, as well as ARMs.
Our choice
We ultimately settled on the Xilinx XC9500XL series since it had a inexpensive advancement set we might utilize to test our JTAG programmer prior to implementing an entire design.
The DO-CPLD-DK from Digilent includes a XC9572XL, a CoolrunnerII, as well as parallel port programmer. Nu Horizons has some old non-ROHS designs for $40, however because of sloppy variable type handling in their credit history card processing scripts, we couldn’t total an order online. We tried to do it over the phone however they refused to take such a little order on the phone, even during a website malfunction. In the end, it was cheaper to pay full cost at Digikey (#122-1512-ND) after including new Horizon’s exorbitant shipping charges. We wouldn’t normally mention this, however with only two locations to buy the board it’s most likely worth noting our experience.
CPLD advancement board
Click right here for a full size schematic picture (PNG). The circuit as well as PCB are designed utilizing the freeware version of Cadsoft Eagle. All the data for this job are included in the job archive linked at the end of the article.
Circuit
A pic 24FJ64GA002 microcontroller (IC1) provides the individual as well as programming interface to the CPLD. We utilize this $4 pic in a great deal of jobs since the peripheral pin choose function makes board routing truly easy. inspect out our introduction to the PIC24F for more details. The pic needs to interact with a PC serial port, so we added an affordable MAX3232 RS232 transceiver. The serial interface should work with a USB->serial adapter.
Our option of CPLD (IC3), a Xilinx XC9572XL (PDF), is linked between the pic as well as a number of other components. We can produce an endless range of circuitry between the pic as well as other chips utilizing the reprogrammable logic inside the CPLD. The pic will program the CPLD with code sent from a PC serial port, however we still brought the JTAG pins to a header for simple outside debugging.
A DS1085 digital programmable oscillator (IC4) produces clock frequencies between 8KHz as well as 133MHz, at 10KHz increments. This is extremely similar to the DS1077 we covered earlier, however it has even steps between all frequencies. The DS1085 needs a 5volt supply (VR2). The I2C interface likewise runs at 5volts, so we linked it to 5volt tolerant pic pins. It’s possible to utilize the 3.3volt 66MHz 1085L instead, as well as eliminate the 5volt supply.
We utilized a inexpensive 3.3volt SOT223 voltage regulator (VR1) to power most of the circuit. The 5volt supply (VR2) can be excluded if you utilize a slower 1085L 3.3volt oscillator.
CPLDs are commonly utilized as a memory controller, so we included 32K of SRAM (IC5) on the advancement board. A 3.3volt latch with 5volt tolerant inputs interface the memory inputs to a wide variety of outside voltages (IC6). The latch inputs are held low with a 1Mohm resistor network (RN1). We’ll discuss this section extensively in an upcoming article.
PCB
The board is a quasi one-sided design. We made a number of compromises so we might prototype this extremely experimental PCB ourselves. We present the board ‘as is’ for other die-hards that may want to etch this board at home. If you send the PCB to a board house, try to correct these problems prior to creating a ‘real’ double-sided board.
One power pin of the CPLD is missing a decoupling capacitor entirely; there was no method to put a capacitor in that area. One CPLD decoupling capacitor, as well as the SRAM decoupling capacitor, are through-hole parts. utilizing these through-hole parts gotten rid of a few jumper wires.
The jumper wires on the back of the board are optimized for single-sided production, rather than great style practices. We faked a double-sided board by soldering the power bus on the back. A genuine double-sided board style should path the power bus to prevent crossing signal paths, as well as include the missing decoupling capacitors.
We utilized an surface install PLCC chip socket, however a through-hole version is definitely a much better idea. We though the SMD version would be simple to solder, however it [turned out to be] a nightmare. We truly desired the CPLD to be on the front of the board for the coolest possible presentation. A appropriate two-sided board with plated through-holes can have a through-hole socket on the front, however this wasn’t possible with our 1-sided prototype board.
Parts list
Click right here for a full size placement diagram (PNG).
Part
Value
IC1
PIC25FJ64GA002 (SOIC)
IC2
MAX3232CSE (SOIC-N)
IC3
XC9572XL-10PCG44C (PLCC)
—
PLCC44 socket, SMD
IC4
DS1085 or DS1085L (SOIC)
IC5
32Kx8, 3.3v, SRAM (SOJ)
IC6
74LVT573D (SOIC)
VR1
3.3v regulator, LD1117S33 (SOT223)
VR2
5v regulator, LD1117S50 (SOT223)
C1-11,13-17
0.1uF decoupling capacitors (0805)
C12
0.01uF capacitor (0805)
C15,16
0.1uF decoupling capacitors (through-hole)
C18
10uF tantalum capacitor (A)
R1,2
390ohm resistor (0805)
R3-5
2000ohm resistor (0805)
RN1
1Mohm resistor network (9 pin)
LED1,2
LED (0805)
X1
db9 female serial port connector *untested
J1
2.1mm power jack
ICSP, JTAG, SV1
0.1″ pin header, right angle
S1
Tactile switch (DTSM-6)
Firmware
The firmware is written in C utilizing the free presentation version of the pic C30 compiler. discover all about working with this pic in our introduction to the pic 24F series. The firmware is included in the job archive at the end of the article.
We desired a super simple method to interact with the hardware on the board without endless compile-program-test cycles. We made a custom version of the Bus Pirate firmware that provides a simple ASCII terminal interface to the DS1085 clock chip (I2C), the CPLD programing interface (JTAG), as well as a 3 cable (SPI) interface to the CPLD. inspect out the Bus Pirate tutorial for background on the simple syntax utilized with the firmware.
The original Bus Pirate firmware handles a number of protocols that share the exact same pins. For the CPLD version, we altered the pin assignments to in shape the connections on the advancement board. We likewise eliminated unused modules as well as options.
CPLD blinky LED examples
We prepared a number of styles in Xilinx’s ISE advancement environment. The schematics, pin placement files, as well as compiled styles (XSVF) are included in the job archive linked at the end of the article. A full explanation of ISE is beyond the range of this article; we discovered the assist data sufficiently useful to make these examples.
The very first style just lights the LED linked to pin 8 of the CPLD.
Prepare the XSVF file
XSVF is a compressed JTAG programming format, as explained by Xilinx in this application note (PDF). XSVF isn’t restricted to programming Xilinx devices, as well as can be gotten ready for any type of chip that provides a typical BSDL JTAG meaning file.
Open the effect programming tool from the ISE style Suite job panel under Configure target device->iMPACT.
select the choice to produce a limit scan file, as well as set the type to XSVF.
Give the XSVF output a data name as well as then add a compiled CPLD picture (ex1.jed) when prompted to add a device.
You should see a JTAG chain that contains a single device.
Click on the gadget as well as select program; effect will record the programming sequences to an XSVF file.
With XSVF data in hand, it’s time to open up a terminal as well as program the CPLD. We like Tera Term as well as Hercules on Windows. You must allow XON/XOFF flow manage in the client to utilize the JTAG interface. The default PC side setting for the advancement board terminal is 115200bps, 8N1.
HiZ>m <–select mode
1. HiZ
2. I2C
3. JTAG
4. RAW3WIRE
MODE>3 <–JTAG
900 mode SET
602 JTAG READY
JTAG>(2) <–probe JTAG chain macro
xxx JTAG INIT CHAIN
xxx JTAGSM: RESET
xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Instruction Register (DELAYED ONE bit FOR TMS)
xxx JTAGSM: IR->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAGSM: DR->IDLE
xxx JTAGSM: RESET
xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAG CHAIN REPORT:
0x01 DEVICE(S)
#0x01 : 0xC9 0x02 0x06 0x9A <–XC9572XL responds
xxx JTAGSM: DR->IDLE
JTAG>
In the terminal we go into the mode menu (m), as well as select JTAG (3). Macro 2 probes the JTAG chain, in our situation this is just the CPLD. The chain report tells us that the chip is linked as well as responding. checked out more about the JTAG interface.
Now we can run the XSVF programmer, macro (3), as well as upload the XSVF data from the terminal in binary mode. The very first example just lights the LED on pin 8. If the LED lights, we can confirm that programming was successful. If your LED doesn’t light, don’t despair; sometimes the JTAG programmer sticks as well as a reset macro (1) will get the chip going.
LED at full brightness.
74LS32/4071 OR gate, blink at half rate (/2)
A major element of the CPLD advancement board is the 1085(L) frequency synthesizer linked to pin 7 of the CPLD. The next example utilizes a logic OR gate, like a 74LS32 or 4071 IC, to blink the LED whenever the clock signal is high. At even the slowest clock rate the blinking will be as well quick to see, however we should get a nice PWM dimming impact compared to the very first example.
JTAG>m <–select mode 1. HiZ 2. I2C 3. JTAG 4. RAW3WIRE MODE>2 <–I2C interface to DS1085 900 mode SET 202 I2C READY I2C>(1) <–address browse macro xxx browsing 7bit I2C address space. Found gadgets at: 0xB0 0xB1 <–found the DS1085 address I2C>
Program the CPLD as before, as well as then switch to I2C mode to gain access to the DS1085 clock. We might look up the gadget address in th